Data networking has become significantly important over the past several years. Information moves form one point to another via wired, wireless, and or optical networks. For example, Local Area Networks (LAN) in many organizations allow for a centralized server, often containing a database, which may be shared by clients. Coupled with the Internet, these LAN systems become Wide Area Networks (WAN) enabling the moving of information worldwide.
Linking together the clients and servers often rely on Network Interface Cards (NICs). These devices may be bridges, routers, switches, and hubs moving data among users, among users and servers, or among servers. Inherent to wired, wireless, and optical networks is data may become distorted as they move from one node to another. The distortion of the data causes errors. Therefore, each of these NICs, bridges, routers, switches, and hubs must “clean up” or retime the data for use either by the device itself, a device attached to it, or for retransmission.
A useful circuit for this is the phase-locked loop (PLL). PLLs accept distorted data, and provide a clock signal and retimed or recovered data as outputs. However, as data rates are approaching one Gigabit and beyond, the ability of PLLs to accept and clean up distorted data becomes compromised.
A number of solutions have been proposed to address the above challenge. A common phase detector used for clock recovery is an Alexander phase detector (otherwise known as a bang-bang phase detector) as described in the article titled, “Clock Recovery from Random Binary Signals by J. D. H. Alexander and published in IEEE Electronics Letters (Vol. 11, pp. 541-542, October 1975). Another phase detector is use is a Hogge phase detector described in the article titled, “A Self Correcting Clock Recovery Circuit” by Charles R. Hogge and published in the IEEE Journal of Lightwave Technology (Vol. LT-3, pp. 1312-1314, December 1985). Both publications are herein incorporated by reference in their entirety.
Both the Alexander and the Hogge phase detector can handle random data patterns at very high data rates. However both require a clock at the same frequency as the data (i.e. 1 bit per clock cycle). As the technology approaches one Gigabit and beyond, generating a clock at such a high frequency becomes problematic.